The present invention relates to a method and/or architecture for implementing a bus interface unit in a microprocessor core generally and, more particularly, to a method and/or architecture for integrating an EJTAG interface with an external bus.
High performance 32-bit and 64-bit Reduced Instruction Set Computer (RISC) processors are an important part of digital consumer electronics, information appliances, set-top boxes, and office automation applications. However, effective debug and development tools for high performance RISC processors remains a concern. Additionally, debugging and hardware/software integration is a significant burden to prototype development and ultimately to market opportunity window.
It would be desirable to provide a method and/or architecture that can reduce die space, complexity and design overhead in the design of integrated circuits.
The present invention concerns an apparatus comprising a processor and an interface. The processor may be configured to support system-on-chip debugging. The interface circuit may be coupled to the processor and configured to interface with an external bus. Reading and writing commands of the processor may be integrated with the system-on-chip debugging.
The objects, features and advantages of the present invention include providing a method and/or architecture for implementing a microprocessor core with a bus interface unit implementing an integrated EJTAG interface that may (i) reduce die space, complexity and overhead; (ii) provide a non-intrusive development and debug technology; (iii) provide real time debug features; (iv) eliminate a need for an independent interface to an external bus; (v) simplify the bus interface unit; and/or (vi) simplify the EJTAG interface.